| 职位编号 | 1101 | 状 态 |
open
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| 职位名称 | 首席工程师 | 工作地点 | 深圳 |
| 行业 | 电子电器 | 年 薪 | 面议万 |
| 工作职责 | •Responsible for full life cycle hardware development, including writing design specifications, detailed board design, component selection, schematic entry and verification, input on chassis level issues, documentation of design and test requirements, board bring-up, testing, debugging, new product introduction, and support. •May perform architectural tradeoff studies and system partitioning. •Will mentor less experienced engineers. | ||
| 职位要求 | •BSEE with MSEE preferred •8+ years experience with detailed architecture, design, debug and test of high speed digital and analog circuits with commercial applications in the telecommunications or data communications industries. •Experience with DDR, PCI-Express, Gigabit Ethernet, 10GbE, and other high-speed bus interfaces. •Experience with debugging tools: oscilloscope, PCI Bus analyzer, logic analyzer, and ICE. •Experience using PADs, Protel, DxDesigner, and/or ORCAD schematic capture tools, including developing layout guidelines and managing layout of high speed design. •Knowledge of EMC, signal integrity, power management and cost sensitivity. •Knowledge of software scripting languages to automate board bring-up and test. •Familiarity with some of the following: Compact PCI card and chassis design for the telecom industry, 10/100/1000 Ethernet circuits, SPARC, Intel Xeon, PowerPC and MIPS family Processors on PCI and compact PCI systems, high availability systems, fluent in VHDL or Verilog. •Familiarity with ATCA, PMC, AMC standards. •Demonstrated strength in working with a team of cross-functional designers to meet aggressive customer requirements and schedules, including DFM and DFT experience. •Excellent communication, teamwork, and basic project leadership skills. | ||
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